Search results for "Nand flash memory"

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Improving MLC flash performance and endurance with extended P/E cycles

2015

The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…

Hardware_MEMORYSTRUCTURESFlash memory emulatorMulti-level cellComputer scienceNand flash memorybusiness.industryLogic gateNAND gateLatency (engineering)businessComputer hardwareFlash file systemGarbage collection2015 31st Symposium on Mass Storage Systems and Technologies (MSST)
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TID and SEE Tests of an Advanced 8 Gbit NAND-Flash Memory

2008

We report on the dose and operational mode dependence of error percentage, stand-by current, erase and write time of 8 Gbit / 4 Gbit NAND-flash memories as well as on their static, dynamic and SEFI cross sections.

Non-volatile memoryHardware_MEMORYSTRUCTURESComputer scienceNand flash memorybusiness.industryGigabitHardware_ARITHMETICANDLOGICSTRUCTURESbusinessComputer hardwareFlash memoryHardware_LOGICDESIGN2008 IEEE Radiation Effects Data Workshop
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